Current Mode Logic (CML) is very popular in high speed link designs, specifically as the final stage of the transmitter's output. During evaluation of CML circuits, it is desired to measure the noise present on the power and ground rails at the circuit to either debug a problem or quantify the magnitude of noise to understand the performance of the CML circuit design.
FIG. 1 illustrates a typical CML differential amplifier used as an off-chip driver in a high speed I/O link. In this design, switchable pull-up resistor networks 110, 111 are used for impedance tuning. Each pull-up resistor network 110, 111 is coupled to ESD protection structures 130, 131 through a T-coil structures 120, 121. The T-coil structures are used to compensate for the capacitance of the ESD protection structures 130, 131. The impedance control pin 140 allows the termination impedance of the circuit to be varied. The bias node 141 allows designation of a particular bias to the circuit.
Traditionally, sense lines are used to measure the noise present on the power and ground rails of the circuit. Sense lines allow a designer or researcher to make measurements in a laboratory; however sense lines suffer a drawback of requiring the addition of C4s and module-to-board connections. Adding C4s and module-to-board connections for this type of application is typically inefficient and ineffective due to the size constraints of the design.